VLSI Design

Design For Testability

Design For Testability is a specialization in the SOC design cycle, which facilitates design for detecting manufacturing defects. With the increase in size and complexity of chips, facilitated by the advancement of manufacturing technologies, Design for Testability has evolved as a specialization in itself over a period of time. In the design for Test Course the importance is given to cover the concepts, methodology thoroughly with the right emphasis on hands-on training, using Synopsys DFT Tools with at least 50% time allocated to lab Sessions.

Duration: 24 weeks
Design For Testability

📚 Course Syllabus

This 24-week comprehensive course is structured to take you from fundamentals to advanced concepts.