Gate Level Simulation

This course is designed to provide a comprehensive understanding of Gate-Level Simulation (GLS) - a critical verification step in the ASIC design flow that ensures the synthesized netlist behaves functionally equivalent to the RTL, meets timing, and integrates correctly with the back-end flow. Learners will gain in-depth knowledge of how GLS fits into the ASIC design and verification lifecycle, focusing on the transition from RTL to synthesized gate-level netlist, and addressing timing verification, power-aware simulation, glitch detection, and X-propagation handling. The course covers functional and timing simulation using Standard Delay Format (SDF), setup for zero-delay and annotated simulations, as well as techniques to debug mismatches between RTL and post-synthesis behavior. It emphasizes practical setup, scripting, waveform analysis, and identifying issues such as uninitialized signals and race conditions. Participants will simulate both clean and X-check-enabled GLS environments using industry tools like VCS, ModelSim, or QuestaSim, and understand how to validate the final netlist before tape-out.